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Synopsis int sub_i2c_hs_rw( sub_handle hndl, int mcode, int count, struct sub_i2c_hs_xfer* px );
Perform High Speed (HS) I2C Master read/write transaction(s) with prior master code transmit according to I2C-bus specification. The whole session has the following format:
At the beginning of the session both master and slave are in Fast Speed or Standard I2C mode. Master issues START condition and transmits Master Code 00001xxx, where xxx is under SW control via mcode parameter. (Master Code 00001000 should not be used as it is reserved by I2C-bus specification for future extensions). Master Code will not be acknowledged - NAK will be generated. At the end of NAK I2C-bus is in HS mode. Now master can perform HS read/write transactions by issuing REPEATED START condition followed by Slave Address with R/W bit and data byte(s) being read/written according to R/W bit. To exit HS mode master issues STOP condition. A number of HS transactions can be performed within single HS mode session (it is recommended by I2C-bus specification). Parameters
struct sub_i2c_hs_xfer { int sa; int r_w; int sz; int act_sz; char data[64]; int status; }; where:
Return value On success function returns 0. Otherwise error code. The "I2C Error" return value means that there was a failure at the master code transmit stage. Results of the HS transactions are reported in status field of the corresponding transaction descriptor. Example /* * Master Code 00001001 * Write 4 bytes to slave 0x44 * Write 2 bytes to slave 0x50 * Read 8 bytes from slave 0x44 */ struct sub_i2c_hs_xfer xfer[3] = { { 0x44, 0, 4, 0, "\x10\x11\x12\x13", 0 }, { 0x50, 0, 2, 0, "\x20\x30", 0 }, { 0x44, 1, 8, 0, "", 0 } };
rc = sub_i2c_hs_rw( hndl, 0x01, 3, xfer, stat );
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