Slave address parameter referenced in I2C related functions is 7 bit number representing I2C slave device address without R/W bit. For example with slave address parameter equal 0x50 slave address stage of the I2C transaction will look like:
I2C EEPROM slave devices may enter internal memory write cycle. Once the internally-timed write cycle has started EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device slave address and R/W bit. Only if the internal write cycle has completed will the EEPROM respond with an ACK, allowing the read or write sequence to continue. Acknowledge polling should be performed on application level. SUB-20 knows nothing about nature of I2C slave device it is connected to.
I2C EEPROMs are usually capable of no more then 64-byte page writes. The internal EEPROM data address lower 6 bits are internally incremented following the receipt of each data byte. The higher data address bits are not incremented, retaining the memory page row location. When the data address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data bytes are transmitted to the EEPROM, the data address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.
High Speed Support
Beginning from FW version 0.3.2 and library version 0.1.12.24, SUB-20 provides High Speed (HS) I2C Master capabilities compliant to "I2C Bus Specification Rev 3.0". HS I2C Master functionality is available via sub_i2c_hs_rw API call. Timing characteristics can be found here HS I2C Master AC Characteristics
Slave Mode
SUB-20 can work in both I2C master and I2C slave modes. Detailed description of I2C slave mode can be found here: SUB-20 as I2C Slave.
Functions